1. Field of the Invention
The present inventive concept relates to static random access memory (SRAM) cells. More particularly, the inventive concept relates to a write assist circuit for operating memory cells.
2. Description of the Related Art
More and more electronic devices demand memory devices and memory cells capable of operating at high speed. Memory devices perform or execute different operations (e.g., read operations, write operations and erase operations) to store data, retrieve stored data, and maintain or manage stored data. Each of these operations requires a certain amount of execution time or “cycle time” to be performed within the memory device which includes a plurality of memory cells. However, the write operation cycle time (i.e., the period of time required to perform a write operation) most directly affects or determines the maximum speed at which a memory device may operate.
Generally, a memory cell is biased by a voltage source and includes at least two PG (pull-gate) transistors and at least two PU (pull-up) transistors. When data is written to a memory cell, one of the PG transistors is turned on to pull down the high voltage node (which is supplied by the voltage source) of the corresponding PU transistor. In other words, the high node connected to the voltage source would collapse. However, if the high voltage nodes of the other PU transistors collapse at the same time, a write failure may occur. In addition, it may need a longer cycle time due to the write failure and for the data to be read from the memory cell. In order to reduce the cycle time of a memory device, a write assist circuit for writing data to a memory cell with a high operation speed is therefore required.